The programme is open to the faculty of engineering colleges, degree colleges, MCA colleges and other allied disciplines in India.
Industry personnel working in the concerned/allied discipline can also attend.
• Sources of Power Dissipation
• Low Power Digital and Analog MOS Circuits:
     - Reducing Glitches
     - Logic Level Power Optimization
     - Standby Mode Leakage Suppression
     - Variable Body Biasing
     - Sleep Transistors
     - Adiabatic Circuits
• Low-Power MOS Circuits Design Techniques:
     - System: Partitioning, Power down
     - Algorithm: Complexity, Concurrency, Regularity
     - Architecture: Parallelism, Pipelining, Redundancy, Data Encoding
     - Circuit Logic: Logic Styles, Energy Recovery, Transistor Sizing
     - Technology: Threshold Reduction, Multithreshold Devices
• Hands on session on the above topics will be provided
Duration: 6 Days
Start Date : 24th – 29th June 2019
Last Date for Submission of application :15th June, 2019
Venue: KL University, Vaddeswaram, A.P
Faculty and Research Scholars | Rs. 2500/- |
Faculty of SC/ST Category | Rs. 1875/- (SC/ ST participants should submit their caste certificate to claim the concession along with application form) |
Industry Participants | Rs. 7500/- |
A filled-in form of application in the prescribed format duly signed and sponsored by appropriate authorities (along with demand draft) should reach the coordinator on or before the last date by post/courier. Participants are requested to write their name and contact number backside of demand draft. It is also mandatory to send scanned application form and demand draft through e-mail to fazalnoorbasha@kluniversity.in as selection will be intimated only through e-mail.
All the outstation selected participants will be provided FREE boarding & lodging in university hostels. No TA will be paid for the participants.
Dr. Fazal Noorbasha
Associate Professor,
Dept. of ECE
K L University
Vaddeswaram, AP - 522502
Mobile: 9000502785
email: fazalnoorbasha@kluniversity.in