The programme is open to the faculty of engineering colleges, degree colleges, MCA colleges and other allied disciplines in Telangana, Andhra Pradesh, Karnataka, Goa, Puducherry and Andaman & Nicobar Islands.
Industry personnel working in the concerned/allied discipline can also attend.
• Describe the general Zynq /
7 Series All Programmable
FPGA architecture
• Understand the Vivado design flow
• Create and debug HDL designs
• Configure FPGA and
verify hardware operation
• Configure FPGA architecture
features, such as Clock Manager,
using the Architecture Wizard
• Use Logic Analyzer to perform
on-chip verification
• ASIC Full custom & Semicustom
IC Design flow using
Mentor Graphics tools
• Design and Verification
concepts using QuestaSim
/ Calibre Tools
Duration: 6 Days
Start Date : 16th – 21st December 2017
Last Date for Submission of application : 08th December 2017
Venue: JNTUA College of Engineering(Autonomous) Anantapuramu
Faculty and Research Scholars from Telangana, Andhra Pradesh, Karnataka, Puducherry, Andaman and Nicobar Islands, Goa | Rs. 2500/- |
Faculty of SC/ST Category from Telangana, Andhra Pradesh, Karnataka, Puducherry, Andaman and Nicobar Islands, Goa | Rs. 1250/- (SC/ ST participants should submit their caste certificate to claim the concession along with application form) |
Industry Participants | Rs. 7500/- |
Participants from other states | Rs. 8500/- |
A filled-in form of application in the prescribed format duly signed and sponsored by appropriate authorities (along with demand draft) should reach the coordinator on or before the last date by post/courier. Participants are requested to write their name and contact number backside of demand draft. It is also mandatory to send scanned application form and demand draft through e-mail to vishnu.ece@jntua.ac.in as selection will be intimated only through e-mail.
All the selected participants will be provided FREE boarding & lodging in the institute guest house. No TA will be paid for the participants
Dr. D. Vishnu Vardhan
Coordinator,
FDP on RECENT ADVANCEMENTS IN XILINX AND ASIC DESIGNS
Department of Electronics & Communication Engineering
JNTUA College of Engineering (Autonomous)
Ananthapuramu - 515002
Andhra Pradesh State, India
Mobile: +91-9440221392
Email Id: vishnu.ece@jntua.ac.in