Dr. SREEHARI RAO PATRI

Associate Professor

Department of Electronics & communication Engineering

National Institute of Technology, Warangal - 506004, Telangana, INDIA

: patri@nitw.ac.in

: 8332969357

Interests: Analog/Mixed Signal IC Design, Power Management IC Design, RF IC Design, On-chip Smart Sensors, Communication Systems

Vision
Motivated and Experienced in the field of IC Design with methodical discipline in system-on-chip design pursuing new academic opportunities. Committed to the development and launch of pioneering research with comprehensive knowledge of my subject matter and delivering the fruits towards the societal needs. I am eager to build on a versatile and goal oriented career in the chosen area of expertise using core skills for the development of student capabilities.


Research Interests


Analog and Mixed Signal IC Design, Power Management ICs, Smart SoC design for IoT applications, Communication Systems, Smart Sensors, SERDES Circuits.


Educational Qualifications


National Institute of Technology, Warangal: Ph.D in Electronics and Comm. Engg (2011).
Thesis: “Design of Power Management Integrated Circuits under Mixed Signal Environment”
Indian Institute of Technology, Roorkee: M.E. in Communication Systems (1995).
Dissertation: “Adaptive Transform Coding of Images”
Nagarjuna University: B.Tech in Electronics and Communication Engineering (1991).
Professional Experience
Thapar University: Faculty, ECE Department [1995-99]
(Instrumental in getting accredited “A” by the NBA)
National Institute of Technology Warangal :
Assistant Professor, ECE Department[1999-2011] [DOJ: 27th May 1999]
Associate Professor in ECE Department] [2011-Till date]

 

Faculty Exchange Program


     Worked with Prof. Bertan’s research group at Arizona State University, USA (Nov.-Dec. 2013)

 

 

 

Message:

ESPRIT DE CORPS

 


Course Taught Previously

 

  • Analog IC Design
  • Mixed SignalIC Design
  • RF IC Design
  • CMOS VLSI Design
  • VLSI DSP Architectures
  • Digital IC Design
  • Digital Communications
  • Digital Switching and Multiplexing
  • Satellite Communications
  • Digital signal processing
  • Probability Theory and Stochastic processes
  • Communications systems


 Courses Currently Being Taught

  • Analog IC Design
  • Analog IC Design Laboratory

Publications

 

Selected List of publications
International Journals:
1. M. Bashir, S. R. Patri and K. S. R. Krishnaprasad, "An ultra-low power, 0.003-mm2 area, voltage to frequency-based smart temperature sensor for -55 oC to +125 oC with one point calibration", Turkish Journal of Electrical Engineering and Computer Sciences, vol. 25(4),pp. 2995-3007, Dec. 2016. [SCI Indexed].
2. M. Bashir, S. R. Patri and K. S. R. Krishnaprasad, "0.5 V, High Gain Two Stage Operational Amplifier with Enhanced Transconductance", International Journal of Electronics Letters, vol. 6(1), pp.80-89, 2018 [SCOPUS Indexed].
3. M. Bashir, S. R. Patri and K. S. R. Krishnaprasad, "A Low Power, High-Accuracy, 1-V CMOS Potentiostat for Amperometric Sensors", Journal of Telecommunication, Electronic and Computer Engineering (JTEC), vol. 9(2-7), pp. 25-32, August 2017 SCOPUS Indexed].
4. M. Bashir, S. R. Patri and K. S. R. Krishnaprasad, "A 0.5-V, Ultra-Low Power Subthreshold Two Stage Gate Driven Operational Amplifier", Journal of Advanced Research in Dynamical and Control Systems, vol. 9(1), 2017 [SCOPUS Indexed].
5. M. Bashir, S. R. Patri and K. S. R. Krishnaprasad, "Low-power voltage to frequency based smart temperature sensor with +0.8/-0.75 oC accuracy for -55 oC to 125 oC" Turkish Journal of Electrical Engineering and Computer Sciences, vol. 25(6), pp. 4880-4892, Sept. 2017 [SCI Indexed].
6. M. Bashir, S. R. Patri and K. S. R. Krishnaprasad, "A low Power, Frequency-to-Digital Converter CMOS based Temperature Sensor in 65 nm Process", VLSI Design and Test.VDAT 2017.Communications in Computer and Information Science - Springer, vol. 711, pp. 657-666, Dec. 2017. [SCOPUS Indexed].
7. M. Bashir, S. R. Patri and K. S. R. Krishnaprasad, "A 159 W, Fourth Order, Multi-Bit, Feedforward, Sigma Delta Modulator for 100 kHz Bandwidth Image Sensors in 65-nmCMOS Process" Radioengineering,Sept. 2017. [Accepted for publication] [SCI Indexed].
8. M A Mushahhid Majeed, S. R. Patri, “Influence of Thickness of Oxide and Dielectric Constant on Short Channel” Journal of Advanced Research in Dynamical and Control Systems, vol. 9(1), 2017 [SCOPUS Indexed].
9. Suresh Alapati, S. R. Patri, “Capacitor less voltage regulator with split drive error amplifier for segmented pass transistors” in Journal of Low Power Electronics. [SCOPUS Indexed].
10. Suresh Alapati, S. R. Patri, “An adaptively biased capacitor less low drop out regulator with improved transient response” Journal of Circuits, Systems and Computers, [SCI Indexed].
11. Patri, Sreehari Rao, and K. S. R. Krishna Prasad. "A robust low-voltage on-chip LDO voltage regulator in 180 nm." VLSI Design 2008 [SCOPUS Indexed].
12. Suresh Alapati, Sreehari Rao P, “ A Low Quiescent Current Fast Settling Capacitor-less Low Drop Out Regulator Employing Multiple Loops”, Indonesian Journal of Electrical Engineering and Computer Science, 10(3), 1070-1079, 2018.[SCOPUS]
13. Suresh Alapati, S. R. Patri, “Improved transient response capacitor less low drop out regulator employing adaptive bias and bulk modulation” in Turkish Journal of Electrical engineering and Computer science. [SCI Indexed].
14. MA Mushahhid Majeed, P Sreehari Rao, "An enhanced grey wolf optimization algorithm with improved exploration ability for analog circuit design automation", Turkish Journal of Electrical Engineering & Computer Sciences, 2018. DOI: 10.3906/elk-1802-110. [SCI Indexed]
15. M A Mushahhid Majeed, Sreehari Rao P, “Optimal Design of CMOS Amplifier Circuits Using Whale Optimization Algorithm” International Conference on Communication, Networks and Computing, Communications in Computer and Information Science - Springer, 2018. [Scopus Indexed] 16. M A Mushahhid Majeed, Sreehari P, “Optimal Design of CMOS Analog Circuit Using Enhanced Grey Wolf Optimization Algorithm”, Journal of Advanced Research in Dynamical and Control Systems, 2018. [Scopus Indexed]
17. M. Bashir and S. R. Patri, "A Low Power, Miniature Temperature Sensor with One-point Calibrated Accuracy of ±0.25 oC from -55 oC to 125 oC in 65 nm CMOS Process", Analog Integrated Circuits and Signal Processing, [SCI Indexed]..
18. M. Bashir and S. R. Patri, "A 9.9 μW, Current to Frequency Based Smart Temperature Sensor in 65 nm CMOS Process with an Inaccuracy of -0.92/+1.15 oC For -55 oC to 125 oC ", International Journal on Smart Sensing and Intelligent Systems, [SCOPUS Indexed]
19. M A Mushahhid Majeed, Sreehari Rao P,” A Hybrid of WOA and mGWO algorithms for Global Optimization and Analog Circuit Design Automation”, COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 2018, [SCI Indexed]
International Conferences:
1. M. Bashir, S. R. Patri and K. S. R. Krishnaprasad, "On-chip CMOS temperature sensor with current calibrated accuracy of -1.1 oC to +1.4 oC (3σ) from -20 oC to 150 oC," 2015 IEEE 19th International Symposium on VLSI Design and Test, Ahmedabad, 2015, pp. 1-5.
2. M. Bashir, S. R. Patri and Krishnaprasad KSR, "MATLAB/SIMULINK based time-domain behavioral modeling of multibit sigma-delta converters," 2016 IEEE International Conference on Computational Techniques in Information and Communication Technologies (ICCTICT), New Delhi, 2016, pp. 132-136.
3. M. Bashir, S. R. Patri and K. S. R. Krishnaprasad, "High speed self-biased current sense amplifier for low power CMOS SRAM0s," 2015 IEEE 19th International Symposium on VLSI Design and Test, Ahmedabad, 2015, pp. 1-5.
4. M. Bashir, S. R. Patri and K. Ksr, "A low power, high accuracy amperometric potentiostat for NOx gas sensors," 2016 International Conference on Next Generation Intelligent Systems (ICNGIS), Kottayam, 2016, pp. 1-4.
5. Alapati, Suresh ; SrihariRao, Patri ; Prasad, K.S.R.Krishna ; Dixit, Saurabh, “A Transient-Enhanced Capacitorless LDO Regulator with improved Error Amplifier”, proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014, 9th-11th July 2014, ISBN:978-1-4799-3763-9
6. P. Kumari, G. Panuganti, S. Alapati and S. R. Patri, "An output capacitor-less cascode flipped voltage follower based low dropout regulator," 2015 Annual IEEE India Conference (INDICON), New Delhi, 2015, pp. 1-4.
7. Suresh Alapati, Sreehari Rao Patri, K.S.R Krishna Prasad, “Transient enhanced LDO Voltage Regulator with improved feed forward path compensation”, ICECE, WASET, Dubai Oct 18th -19th 2014
8. Debasish Dwibedy , Suresh Alapati , Sreeharirao Patri ,Krishnaprasad KSR, “Fully on Chip Low Dropout (LDO) Voltage Regulator with Improved Transient Response” , IEEE TENCON 2014, 22nd -25th Oct 2014, Bangkok
9. Suresh A, Sreeharirao Patri, Debasish Dwibedy, Sunil kumar Bhat, Gaurav K, Krishnaprasad KSR, “Fully on chip Area efficient LDO voltage regulator”, IEEE TENCON 2014, 22nd -25th Oct 2014, Bangkok
10. Pavan Kumar Sharma Devulapalli, Patri Sreehari Rao and Ksr Krishna Prasad. A Low Phase Noise 10-G bits/s Clock and Data Recovery Circuit with Modified D Latch For Backplane Applications Using Dual Loop Architecture
11. Suresh A, Sreehari Rao Patri, Saurab Dixit, “A low Drop out regulator with improved compensation technique for fast transient response ”, 1st International conference on Microelectronics, Circuits and systems-MICRO 2014, Kolkata India
12. Pavan Kumar Sharma Devulapalli, Patri Sreehari Rao,“Power optimized PLL implementation in 180nm CMOS technology”, VDAT 2014, Coimbatore.
13. Suresh A, Sreehari Rao Patri, Krishnaprasad KSR, “250mA ultra low drop out regulator with high slew rate double recycling folded cascode error amplifier”, in Proc. IEEE 18th Int. Symp. On VLSI Design and Test, 16th – 18th July 2014, pp.1-5.
14. P. S. Rao and K. S. R. Krishna Prasad, "ON chip LDO voltage regulator with improved transient response in 180nm," 2008 International Conference on Electronic Design, Penang, 2008, pp. 1-6.
15. Utkarsh Rastogi, Anuradha, Rathod Chandra Shekar, Shubham Singh and P. Sri Hari Rao, “Optimal Chaotic Sequences for DS-CDMA Using Genetic Algorithm”, IEEE WiSPNET 2017.
16. M. A. Mushahhid Majeed and P. S. Rao, "Optimization of CMOS analog circuits using sine cosine algorithm," IEEE 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Delhi, 2017, pp. 1-6. 17. M A Mushahhid Majeed, Sreehari Rao P, “Optimization of CMOS Analog Circuits Using Grey Wolf Optimization Algorithm”, IEEE INDICON 2017, IIT Roorkee. . 18. M A Mushahhid Majeed, Sreehari Rao P, “Optimal Circuit Sizing of CMOS Operational Amplifier Using Modified Grey Wolf Optimization Algorithm”, IEEE-International Conference on Innovative Technologies in Engineering 2018, Osmania University, Hyderabad.

PHDs Supervised

Two PhDs supervised. 

 


Workshops/Conferences

1. 5 day FDP on, “Digital communications and FEC coding techniques” (2016).
2. 10 day FDP on, “Aspects of IC Design” (2016).
3. 10 day FDP on, “Digital VLSI Circuit Design” (2017).
4. 5 day GIAN program on, “Advanced CMOS Clock Generation Circuits” (Dec. 2017).
5. Two 6 day FDP on, “CMOS analog IC design” at SRKR Engg college and VRSEC
6. Four 7 day FDPs at ANITS Vizag, NRIIT Vijayawada, Aeronautical institute of Technology, Dundigal on “5G comm.” and at VRSEVC on “CMOSIC for Instrumentation and IoT”

7. Six day FDP on Signal Processing for 5G Wireless Communications at Institute of Aeronautical Engg, Hyderabad.

8.  Six day FDP on   Recent Trends in IC Design and its Applications at Sasi Institute of Technology Tadepalligudem

9.  Six day FDP on  Mixed VLSI System Design using CADENCE Tools at RGIT, Nandyal

10. Six day FDP on  DNA of Mixed Signal IC design for Portable Systems at NIT Warangal

Projects

R&D Projects
1. Principal inves
tigator of the project, “Design of 14 bit ADC with high analog voltage input” with RCI, DRDO, Hyderabad. [Rs 10 lakhs appx] [Completed]
2. Principal Investigator of the defense project, “Design of on-chip LDO voltage regulator” with ANURAG DRDO, Hyderabad [Rs 10 lakhs appx.][Completed]
3. Principal Investigator of the defense project “Implementation of DLC receiver using improved performance DSCDMA” with RCI DRDO Hyderabad.[Rs 10 lakhs appx.][Completed]
4. Principal Investigator of the defense project, “Optimizing Chaotic code set for DLC receiver with verification on FPGA”, with RCI DRDO Hyderabad. [Rs 10 lakhs appx.] [Under progress]
5. Principal Investigator of the project “Design of CMOS readout circuit MEMS capacitor accelerometers”, sponsored by RCI Hyderabad. [Rs 10 lakhs appx.] [Under progress]
6. Chief Investigator of MeiTY sponsored project SMDP Chip 2 Systems. [Under progress]: Designed and sent for fabrication the power management segment and the smart temperature sensor for the smart probe for ADA in collaboration with IISc Bangalore.
7. Principal Investigator  of the project "Advanced CMOS Clock generation  circuits"  MHRD sponsored SPARC project  in association with prof Pavan kumar Hanumolu, University of Illinoisat Urbana Champiagn [UnderProgress]

 

Awards and Honors

 

Additional Responsibility

1. Vice Chairman Admissions NIT Warangal [2018 May to till date]
2. Faculty advisor, ECE Association, NITW [2011-2014]
3. Mess and block Warden, NITW [2011-2014]
4. Faculty advisor M.Tech VLSI SD [2010-2016]
5. Faculty incharge of Stores, ECE Department [2014 to till date]
6. Faculty advisor for E&AHAM club [2015 to 2018]
7. Monitoring committee member for E& ICT academy [Oct. 2017 to till date]