Vadthiya Narendar

Assistant Professor

Department of Electronics & communication Engineering

National Institute of Technology, Warangal - 506004, Telangana, INDIA

: narendarv@nitw.ac.in

: 9795235922

Interests: Beyond CMOS, Nanoscale device design and modeling, Modeling and simulation of semiconductor devices, 2D material based devices, VLSI Circuits & Systems.

 

Educational Details

Course Attended

College/University

Discipline/Topic

Year of Completion

Ph.D.

MNNIT Allahabad, U.P., INDIA

Nanoelectronic Devices (FinFETs)

2016

M. Tech.

MNNIT Allahabad, U.P., INDIA

Microelectronic & VLSI Design

2010

B. Tech.

Sri Venkateswara Engineering College-Suryapet/ JNTU, Telangana, INDIA

Electronics & Communications Engineering

2006

 

Work Experience

  • Assistant Professor, From May 11, 2018 to till date, Department of Electronics and Communication Engineering, National Institute of Technology Warangal (NITW), Telangana-INDIA
  • Assistant Professor,  From October 15, 2012 to May 10, 2018, Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology (MNNIT) Allahabad, Uttar Pradesh, INDIA
  • Assistant Professor, From July 27, 2010 to October 5, 2012, under SMDP-II Project in Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology (MNNIT) Allahabad, Uttar Pradesh, INDIA

     


 

 

 

 

Course Taught Previously

 Course Taught in U. G. Level at NIT Warangal (June 2018- till date)

S. No

Name of the Course

1
Nanoelectronics Device and Materials (EC5207)
2CMOS VLSI Design (EC303)
3Digital System Design-II (EC251)
4Digital System Design-I (EC201)
  

Course Taught in P. G. Level at MNNIT Allahabad (Oct. 2012 - May 2018)

S. No

Name of the Course

1

Digital IC Design (EC2204)

2

VLSI Technology and Process Modeling (EC2203)

3

VLSI CAD

 

Course Taught in U. G. Level at MNNIT Allahabad (Oct. 2012 - May 2018)

S. No

Name of the Course

1

Principles of Electronics (EC1304)

2

Analog and Digital Electronics (EC1303)

3

Digital Electronics (EC1402)

4

VLSI Technology (EC1501)

5

Digital Electronics and Microprocessor (EC1881)

6

Microwave Semiconductor Devices and Applications (EC713)

7

Computer Organization  (CS507)

8

Communication foundations (EC1405)

 

Publications

 Journals

  1. Bharath Sreenivasulu V. and Vadthiya Narendar, "Design and Temperature Assessment of Junctionless Nano-Sheet FET for Nanoscale Applications", AEU - International Journal of Electronics and Communications, Accepted, May 2021, 153803 (Impact factor: 2.924)
  2. Bharath Sreenivasulu V. and Vadthiya Narendar, "Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications", Silicon Journal, Accepted, May 2021.  (Impact factor: 1.499)
  3. Bharath Sreenivasulu V. and Vadthiya Narendar, "A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length", Silicon Journal, Accepted, Feburary 2021.  (Impact factor: 1.499)
  4. Bharath Sreenivasulu V. and Vadthiya Narendar, "Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications", ECS Journal of Solid State Science and Technology, Vol. 10, Issue. 1, pp. 013008, January 2021.  (Impact factor: 2.142)
  5. Vadthiya Narendar, Pallavi N., V Bheemudu, B.  Sunitha “A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance”, AEU - International Journal of Electronics and Communications, Volume 127, December 2020, 153459 (Impact factor: 2.924)
  6. V. Narendar, P. Narware, V. Bheemudu and B. Sunitha, "Investigation of Short Channel Effects (SCEs) and Analog/RF Figure of Merits (FOMs) of Dual-Material Bottom-Spacer Ground-Plane (DMBSGP) FinFET", Silicon Journal , Vol. 12, Issue. 10, pp. 2283-2291, October 2020 (Impact factor: 1.246)
  7. Vadthiya Narendar, and Kalola Ankit Girdhardas, "Surface potential Modeling of Graded-channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study," Silicon Journal  Vol. 10, Issue.6, pp. 2865-2875, 2018 (Impact factor: 1.246)
  8. Vadthiya Narendar, K. Gupta and Shikhar Saxena, "First Principle Study of Doped Graphene for FET Applications", Silicon Journal  Vol. 11, Issue. 1, pp. 277–286 (2019). https://doi.org/10.1007/s12633-018-9852-x (Impact factor: 1.246)
  9. Vadthiya Narendar "Performance Enhancement of FinFET Devices with Gate-Stack (GS) High-K Dielectrics for Nanoscale Applications",  Silicon Journal  Vol. 10, Issue.6, pp. 2819-2829, 2018 (Impact factor: 1.246)
  10. Vadthiya Narendar, Shweta Tripathi and R. Bhavani Shankar Naik, "A Two-Dimensional (2D) Analytical Modeling and Improved Short Channel Performance of Graded-Channel Gate-Stack (GCGS) Dual-Material Double-Gate (DMDG) MOSFET", Silicon Journal  Vol. 10, Issue. 6, pp. 2399-2407, 2018 (Impact factor: 1.246)
  11. Vadthiya Narendar, Saurabh Rai and Siddharth Tiwari, "A two-dimensional (2D) analytical surface potential and subthreshold current model for underlap dual-material double-gate (DMDG) FinFET", Journal of Computational Electronics, 15, Issue 4, pp. 1316 - 1325, December 2016. (Impact factor: 1.56)
  12. Vadthiya Narendar, Saurabh Rai, Siddharth Tiwari and R.A. Mishra, "A two-dimensional (2D) analytical subthreshold swing and transconductance model of underlap dual-material double-gate (DMDG) MOSFET for analog/RF applications", Superlattices and Microstructures, 100, pp. 274-289, 2016. (Impact factor: 2.12)
  13. Vadthiya Narendar and R. A. Mishra, "Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs)", Superlattices and Microstructures, 85, pp. 357-369, 2015. (Impact factor: 2.12)
  14. Shweta Tripathi and Vadthiya Narendar, "A three-dimensional (3D) analytical model for subthreshold characteristics of uniformly doped FinFET", Superlattices and Microstructures, 83, pp. 476-487, 2015. (Impact factor: 2.12)
  15. L. Tripathi, Ramanuj Mishra, V. Narendar, and R. A. Mishra, "Optimization of pie-gate Bulk FinFET structure",  International Journal of Computer Applications (0975 - 8887) Volume 59, No.2, December 2012.
  16. V. Narendar, Ramanuj Mishra, Sanjeev Rai, Nayana R, Suman Lata Tripathi and R. A. Mishra, "THRESHOLD VOLTAGE CONTROL SCHEMES IN FINFETS",  International Journal of VLSI Design & Communication Systems (VLSICS) AIRCC Vol.3, No.2, April 2012.
  17. V. Narendar, Wanjul Dattatry, Sanjeev Rai and R. A. Mishra, "Design of High-Performance Digital Logic Circuits using FinFET Technology",  International Journal of Computer Applications (IJCA) (0975 - 8887) Volume 41, No.20, March 2012.

 

  • Conferences
  1. Vadthiya Narendar and Ashutosh Kumar Pandey “Impact of Dimensional Effects on Subsurface Leakage Current of a Low-VTH Nanoscale MOSFET under Accumulation Bias” VCAS 2018 International Conference on VLSI, Communication and Signal Processing, November 29-December 1, 2018, MNNIT Allahabad, Utter Pradesh, India.
  2. Vadthiya Narendar, Richa Parihar and Ashutosh Kumar Pandey “Short Channel Effects (SCEs) Based Comparative Study of Double-Gate (DG) and Gate-All-Around (GAA) FinFET Structures for Nanoscale Applications” VCAS 2018 International Conference on VLSI, Communication and Signal Processing, November 29-December 1, 2018, MNNIT Allahabad, Utter Pradesh, India.
  3. Vadthiya Narendar, Shrey and Naresh Kumar Reddy B., "Performance Enhancement of Multi-Gate MOSFETs Using Gate Dielectric Engineering", GUCON 2018 : IEEE International Conference On Computing, Power And Communication Technologies 2018, September 28-29, 2018, Greater Noida, Uttar Pradesh, India.
  4. Richa Parihar, Vadthiya Narendar and A. Mishra, "Comparative Study of Nanoscale FinFET Structures for High-K Gate Dielectrics", IEEE International Conference on Devices, Circuits and Communications (ICDCCom-2014),  12-13 Sept. 2014, BIT Mesra, Ranchi, India
  5. Manish Kumar Rai, Vadthiya Narendar and A. Mishra, "Significance of variation in various parameters on electrical characteristics of FinFET devices", 2014 IEEE Students Conference on Engineering and Systems (SCES), 28-30 May 2014, MNNIT Allahabad, U.P, India.
  6. L. Tripathi, Ramanuj Mishra, V. Narendar, and R. A. Mishra, "High performance Bulk FinFET with Bottom Spacer" 2013 IEEE International Conference on Electronics, Computing, Communication Technologies (CONECCT), on 17-19 January 2013, Bangalore, Karnataka, India.
  7. Bhanu Chander D, Narendar Vadthiya, Alok Kumar and R. A. Mishra, "Suppression of Short Channel Effects (SCEs) by Dual Material Gate Veritical Surrounding Gate (DMGVSG) MOSFET: 3-D TCAD Simulation", International Conference On DESIGN AND MANUFACTRING, IConDM 2013, Jul 18, 2013 - Jul 20, 2013, IIITDM Kancheepuram, Chennai, India
  8. V. Narendar, Sanjeev Rai, R. A. Mishra and A.K.Singh, "Performance evaluation of underlap double-gate and double-metal gate FinFET device for nanoscale applications", International Conference on Emerging Trends in Electrical, Electronics and Communication Technologies-ICECIT, 2012, on 21-23 December 2012, Anantapur, Andhra Pradesh, India.
  9. Shivshankar Mishra, V. Narendar and R. A. Mishra, "On the Design of High-Performance CMOS 1-Bit Full Adder Circuits" International conference on VLSI, Communication and Instrumentation (ICVCI-11), April 7-9, 2011, Kottayam, Kerala, India.
  10. V. Narendar, S. Wairya, R.K.Nagaria and S. Tiwari,  "Design of High-Performance CMOS 1-Bit Full Adder Circuits for VLSI Applications",  International Conference on Advances in Electrical & Electronics Engineering (ICAEEE-2011) on February 25-26, 2011 at Moradabad Institute of Technology (MIT) Moradabad, U.P, India.
  11. Wairya, P. K. Tripathi, V. Narendar, R. K. Nagaria and S. Tiwari, "A New High Performance Adder-Cell Design and Analysis with minimum Transistors",  Nirma University International Conference on Engineering (NUiCONE) 2010 on current trends in technology, 9-11 December 2010, Nirma University, Ahmadabad, India.
  12. V. Narendar, S. Wairya, R.K.Nagaria and S. Tiwari, "Comparative study of High-Speed full adder cell for Low-Voltage" International Conference of Recent Advances in e-Communication and i-Technologies (REACT-2010-OPPNET), pp-90, 29th & 30th April 2010, Chennai, India.

PHDs Supervised

PhD Supervised

On going:

1. Bharath Sreenivasulu (718144)

2. Santosh Kumar Padhi (701940)

3. Ravi Kothapally (701934)

 

PG Projects

The list of PG projects under my supervision at MNNIT Allahabad

S. No

Title of the Project

Name of the Student

Year of Completion

1

Investigation and Design of Nanoelectronic Devices for Biosensor Applications

Neha Bage (2016VL04)

2018

2

Performance Enhancement Techniques in FinFET Device Structure

G Palguna Kumar Reddy

(2015VL11)

2017

3

Investigation of Short Channel Effects in Double-Gate (DG) MOSFETs

Anjani Kant (2015EL03)

2017

4

Analytical Modeling and Simulation of Multigate Devices

Pallavi Narware (2014VL08)

2016

5

 

Analytical Modeling and Simulation of high-K Dual Metal Double-Gate (DMDG) MOSFET

Kalola Ankit Girdhardas

(2014VL12)

2016

6

Modeling and Simulation of Channel Engineered DG MOSFETs

Ramavathu Bhavani Shankar Naik

(2014VL14)

2016

7

3D Numerical Simulation based Analog and RF Performance Comparison of FinFET Devices

Ashutosh Kumar Varun

(2013EL19)

2015

8

3D Simulation andAanalytical Potential Model of Tri-Gate FinFET for Nnoscale Applications

Richa Parihar (2012VL01)

2014

9

Modeling of Multigate FET Device Characteristics considering Dielectric Pocket for Nanoscale Application

Pallavi Gupta (2012VL15)

2014

10

Comparative Study of CMOS Devices based on 3D Simulation and Analytical Modeling

Manish Kumar Rai (2012VL03)

 2014

 

UG Projects

The list of UG projects under my supervision at MNNIT Allahabad

S. No

Title of the Project

Name of the Students

Year of Completion

1

Analytical Modelling and Simulation of Gate All Around Multi Gate MOSFET and TFET devices

Suvrat Krishna Mishra (20149030)

Priyanka Rai (20145107)

Sudhakar Pratap (20145102)

2018

2

Analytical Modelling and Simulation of Cylindrical Gate All Around MOSFET

Rishabh Kumar Upadhyay (20145026)

Deepshikha Katiyar (20148055)

Matari Sachit Raj (20143131)

2018

3

Trapping and Thermal Effects Analysis of

AlGaN/GaN HEMTs

Puneet Kumar (20145046)

Yedla Jagadeesh (20145111)

Pankaj Rawat (20125086)

2018

4

Investigation of charge plasma (CP) based dual-material double-gate (DMDG) MOS devices

Mohd Salman, Kajal Kapoor and Kanchan Bharti

2017

5

Comparative study of subthreshold characteristics of SSOI and SSGOI MOSFETs with dual spacer high-K dielectric

Raunak Agarwal, Rajat Barman and Jitendra Kumar Singh

2017

6

Performance enhancement of underlap gate engineered MOSFETs

Piyush, Bhavana Shreeram and Vipin Kumar

2017

7

Analytical Modeling and Simulation of Channel Engineered MOSFET

Saurabh Rai, Shubham Anand V. and Prashant Singh

2016

8

Analytical Modeling and Simulation of Junctionless Nanowire Transistor

Siddharth Tiwari, Ankit Singh K., Deepak Kumar

2016

9

Design and Simulation of FinFET under Analog and RF performance considerations

Apurva Chaudhary, Varenyam and Rakesh Kumar Yadav

2015

10

Simulation Study of Graphene Transistors

Shikhar Saxena and Shivam Sharma

2015

11

Performance analysis of hetero-structure Double-Gate MOSFET

Nitish Prakash, Ankit Singh and Rohit Verma

2015

12

A 3D Simulations and Analysis of independent gate FinFET and multi channel NWFET

Abhishek Saurav, Nishant Kumar and Aditi Kulshrestha

 

2014

13

DTMF based home automation system using mobile phone

Ashish Ranjan, Amit Meena and Jitendra Kumar

 

2014

14

SERF and Modified SERF Adder for Ultra Low-Power Consumption

Ayush, Chetan Dorji and Rich Dhyani

2014

 

Workshops/Conferences

 

Seminars/Workshop/Conferences/STC/FDP/QIP/Summer Training etc. Organized and participated

 

S. No.

Title

Venue

Duration/Period

Organized/ Participated

1

4th India ESD Workshop (InEW 2020)

IISc Bangalore

26th-27th Feb., 2020

Participated

 2

Advanced CMOS VLSI

NIT Warangal

3-8 December,  2018

Organized

3

Role of IPR in Innovation Management for Academia – Industry Collaboration Organized by NRDC New Delhi and NIT Warangal  

NIT Warangal

17th November,  2018

 Participated
 4

Induction Training Programme  (Phase-II)

 NIT Warangal 17th – 22nd September, 2018 Participated
5

Induction Training Programme  (Phase-I)

NIT Warangal

11th – 30th June, 2018

Participated

6

VLSI Design and Embedded Systems (VDES-2017)

MNNIT Allahabad

14th June -15th July 2017

Organized

7

INUP Familiarization Workshop Nanofabrication Technologies organized by CeNSE, IISc Bangaluru

MANIT Jaipur

26th - 27th August

2016

Participated

8

VLSI Design and Embedded Systems (VDES-2016)

MNNIT Allahabad

13th June - 14th July 2016

Organized

9

Modeling, Simulation and Characterization of Nano-Transistors

IIT Kanpur

26th - 30th October 2015

Participated

10

VLSI Design and Embedded Systems

MNNIT Allahabad

12th June - 14th July 2013

Organized

11

VLSI Design and Embedded Systems

MNNIT Allahabad

13th June - 14th July 2012

Organized

12

Design Finishing for Chip Tape-Out Organized by IIT Bombay

VNIT Nagpur

8th  - 10th  October 2011

Participated

13

VLSI Design and Communication Related Softwares

MNNIT Allahabad

12th June - 15th July 2011

Organized

14

Low Power, Low Noise Operational Amplifier Design using Cadence flow

IIT Delhi

14th - 19th  March 2011

Participated

 

Projects

Projects at NIT Warangal

S. No.

Funding Agency

Project Title

Budget (Rs.)

Duration

1.

RSM (NIT Warangal)

Analytical Modeling, Simulation and Performance Enhancement of Engineered MOSFETs

5.0 Lac

2018-2020

 

 On going (SMDP-C2SD) at MNNIT Allahabad

1.  Advanced Video Decoder for Mobile Telemedicine

 

Awards and Honors

 

Additional Responsibility

Academic/Administrative

 

  • In-charge Electronic Design Automation (EDA) Lab ECED, NIT Warangal (July 01, 2018 – till date)
  • 2/4 B.Tech Course Coordinator ECED, NIT Warangal (July 01, 2018 – till date)
  • Coordinator Avishkar-2017 (Technical Festival of MNNIT Allahabad)
  • Convener, Electronic Society & Student Welfare Committee ECED, MNNIT Allahabad (Sept. 2017 - May 7, 2018)
  • Convener, RTI related matter ECED, MNNIT Allahabad (Sept. 2017 - May 7, 2018)
  • Warden, S. V. Patel Hostel, MNNIT Allahabad (Feb. 13, 2017 - May 10, 2018)
  • O. C. Examination ECED, MNNIT Allahabad (Feb. 2017 - May 7, 2018)
  • O. C. VLSI Lab ECED, MNNIT Allahabad (15 Oct. 2015 - 15 Oct. 2017)
  • Member, DMPC ECED, MNNIT Allahabad (2014 - Sept. 2017)
  • Member, DUGC ECED, MNNIT Allahabad (2015 - Sept. 2017)
  • Observer in Department Doctoral Selection Committee (DDSC) of Department of Computer Science and Engineering for Session 2014-2015 (Odd and Even Semester) at MNNIT Allahabad
  • Observer in Department Doctoral Selection Committee (DDSC) of Department of Computer Science and Engineering for Session 2015-2016 (Odd and Even Semester) at MNNIT Allahabad
  • Observer in Department Doctoral Selection Committee (DDSC) of Department of Biotechnology for Session 2016-2017 (Even Semester) at MNNIT Allahabad

 

 Other Activities

  • Session Chair:  VCAS-2020 3rd International Conference on VLSI, Communication and Signal Processing, 9-11 October, 2020, MNNIT Allahabad
  • Reviewer: VCAS-2020 3rd International Conference on VLSI, Communication and Signal Processing, 9-11 October, 2020, MNNIT Allahabad
  • Session Chair:  International Conference on Communications, Signal Processing and VLSI (IC2SV2019), 23-24, October 2019, NIT Warangal
  • Reviewer:  IInternational Conference on Communications, Signal Processing and VLSI (IC2SV2019), 23-24, October 2019, NIT Warangal
  • Reviewer: VCAS-2019 Second International Conference on VLSI, Communication and Signal Processing, 21-23 October, 2019, MNNIT Allahabad
  • Reviewer: VCAS 2018 International Conference on VLSI, Communication and Signal Processing, MNNIT Allahabad
  • Session Chair: 2013 2nd Students'  Conference on Engineering and Systems (SCES 2013) April 12-14, 2013, at MNNIT Allahabad
  • Reviewer of 2013 2nd Students' Conference on Engineering and Systems (SCES 2013), MNNIT Allahabad
  • Reviewer of 3rd Students' Conference on Engineering and Systems (SCES 2014), MNNIT Allahabad
  • Reviewer of International Conference on Power, Control and Embedded Systems (ICPCES) 2014, MNNIT Allahabad
  • Reviewer of 4th Students' Conference on Engineering and Systems (SCES 2015), MNNIT Allahabad
  • Reviewer of International Journal of Computational Electronics, Springer Publications
  • Reviewer of International Journal of Silicon, Springer Publications
  • Reviewer of Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers